Field of the Invention
This invention relates to systems and methods for implementing a low density parity check (LDPC) decoding algorithm.
Background of the Invention
In flash memories, a read operation returns one bit for each cell of a page. With processors becoming smaller and smaller in order to scale down power and increase capacity, the data has become noisier and noisier. To effectively combat ever greater noise, the next generation controller technology is migrating from conventional BCH coding to the capacity approaching LDPC coding. For practical application of high rate (>0.8) codes, LDPC hard correction capability is not much different from that of BCH codes, however, in case of hard read failure, multiple reads may be combined to enable efficient LDPC soft decoding, whereas efficient soft decoding of BCH codes has not been discovered up-to-date.
In conventional LDPC decoding, multiple reads are combined to generate parameters used to perform soft decoding of a parity code. However, this is computationally expensive and therefore costs time and power.
The systems and methods disclosed herein provide an improved approach for performing soft decoding of an LDPC code.